1. Field of the Invention
Embodiments of the present invention generally relate to automatic generation of data storage for multi-threaded processing and, more specifically, to a multi-threaded first-in first-out (FIFO) memory.
2. Description of the Related Art
Integrated circuits designed to process data typically use FIFO memories to store data between processing stages. These FIFO memories may have different widths, depths, and different input and output clock frequencies. Conventionally, generators that produce synthesizable code have been used to efficiently produce different variations of FIFO memories. More recently, multi-threaded processing systems use a separate FIFO memory to store data for each processing thread. Using separate FIFOs permits data for a thread to be accessed independently from data for another thread. This independence is essential since during multi-threaded processing, each thread may be executed at a different rate and data may be stored in or read from the FIFOs at different rates. However, using separate FIFOs for each thread uses more die area than using a single FIFO to store data for multiple threads. The conventional generators do not produce synthesizable code for a FIFO that may be used to store data for multiple threads and allow the data for each thread to be accessed independently.
Accordingly, there is a desire to use a FIFO memory generator to produce synthesizable code for a shared FIFO to store data for multiple threads.